With the development of semiconductor industry, sizes of semiconductor components have been in nanometers. Thus, a gate dielectric layer of a metal oxide semiconductor (MOS) transistor becomes thinner and thinner with the decrease of a size of a channel. However, if a thickness of the gate dielectric layer is too thin, a current leakage will generated badly, thereby affecting the performance of the MOS transistor and increasing power energy consumption. Therefore, currently, a gate structure including an insulating layer with high dielectric constant (high-K) has been widely used. Such gate structure can reduce a current leakage, thereby improving the performance of the MOS transistor. Additionally, the insulating layer with high dielectric constant is generally cooperated with a metal gate so as to reduce a resistance of the gate structure. In order to improve the thermal stability of the gate structure and to prevent a reaction of the metal gate and the insulating layer with high dielectric constant, a barrier layer is generally disposed between the metal gate and the insulating layer with high dielectric constant. For example, the barrier layer can be made of titanium nitride (TiN). However, during manufacturing the gate structure with the barrier layer, the non-planarity of a surface of the gate structure will occur, thereby affecting the quality of the MOS transistor.
Therefore, what is needed is to a planarization method applied in a process of manufacturing a semiconductor component to overcome the above disadvantages.